Adding the iaddq instruction to the SEQ processor


In this lab you will become ams and become familiar with the Y86-64 tools by extending the SEQ (sequential) Y86-64 processor simulator with a new instruction, iaddq. This instruction will will be helpful to you in writing your programs.


From one of the CS machines, download and extract the archlab.tar starter code.

cd cs224
tar xvf archlab.tar
cd archalb

Adding an Instruction to the SEQ Processor

You will be working in directory sim/seq for this lab. Your task is to extend the SEQ processor to support the iaddq V, rB instruction, which adds the constant value V to the destination register rB. To add this instruction, you will modify the file seq-full.hcl, which implements the version of SEQ described in the textbook. In addition, it contains declarations of some constants that you will need for your solution.

Byte         |   0   |   1    |   2    |   3    |   4    |   5    |   6    |   7    |   8    |   9    | 
iaddq V, rB  | C | 0 | F | rB |                                   V                                   |

Your HCL file must begin with a header comment containing the following information:

Instruction irmovq V, rB

Fetch       icode:ifun <- M1[PC]
                rA:rB <- M1[PC+1]
                valC <- M8[PC+2]
                valP <- PC + 10


Execute     valE <- 0 + valC


Write back  R[rB] <- valE

PC update   PC <- valP
Instruction OPq rA, rB

Fetch       icode:ifun <- M1[PC]
                rA:rB <- M1[PC+1]
                valP <- PC + 2

Decode      valA <- R[rA]
                valB <- R[rB]

Execute     valE <- valB OP valA
                Set CC


Write back  R[rB] <- valE

PC update   PC <- valP


Once you have wrote down the description for the computation of the iaddq instruction have a Coach verify your solution.

Implementing the instruction

Now you are ready to add the instruction to the seq-full.hcl file. Use the above description as your guide. Look for places where you will need to add the IIADDQ instruction code.

Building and Testing Your Solution

Once you have finished modifying the seq-full.hcl file, then you will need to build a new instance of the SEQ simulator ssim based on this HCL file, and then test it.

You can use make to build a new SEQ simulator.

make VERSION=full

This builds a version of ssim that uses the control logic you specified in seq-full.hcl. To save typing, you can assign VERSION=full in the Makefile.

Testing your solution on a simple Y86-64 program

For your initial testing, I recommend running simple programs such as asumi.yo (for testing iaddq) in TTY (non gui) mode, comparing the results against the ISA simulation:

./ssim -t ../y86-code/asumi.yo

If the ISA test fails, then you should debug your implementation by single stepping the simulator in GUI mode:

./ssim -g ../y86-code/asumi.yo

Retesting your solution using the benchmark programs

Once your simulator is able to correctly execute small programs, then you can automatically test it on the Y86-64 benchmark programs in ../y86-code:

(cd ../y86-code; make testssim)

This will run ssim on the benchmark programs and check for correctness by comparing the resulting processor state with the state from a high-level ISA simulation. Note that none of these programs test the added instruction. You are simply making sure that your solution did not inject errors for the original instructions. See file ../y86-code/README file for more details.

Performing regression tests

Once you can execute the benchmark programs correctly, then you should run the extensive set of regression tests in ../ptest. To test everything except iaddq:

(cd ../ptest; make SIM=../seq/ssim)

To test your implementation of iaddq:

(cd ../ptest; make SIM=../seq/ssim TFLAGS=-i)

For more information on the SEQ simulator refer to the CS:APP3e Guide to Y86-64 Processor Simulators.

Submitting your work

Upload your seq-full.hcl to Gradescope.