Lab10 Quiz Study Guide
Pipelining Core Concept
Divide long combinational logic into smaller independent stages, separated by pipeline registers.
Clock rate limited by longest pipeline stage.
Pipelining divides instruction execution into 5 stages (IF → ID → EX → MEM → WB), overlapping multiple instructions to increase throughput while slightly increasing latency due to pipeline register overhead.
Key metrics: Throughput and Latency. In our pipelined architecture, each instruction has a latency of 5 cycles. Assuming no bubbles are injected, the throughput is one instruction per cycle.
The 5 Stages
| Stage | What happens |
|---|---|
| IF | Fetch instruction from memory using PC; compute PC+4 |
| ID | Decode instruction, read registers, extract immediate |
| EX | ALU operation, branch evaluation, jump target calculation |
| MEM | Read/write data memory (loads and stores) |
| WB | Write result back to register file |
Hazards & Solutions
Data Hazard (RAW): A later instruction reads a register that an earlier instruction hasn’t written yet. → Forwarding bypasses the value from EX, MEM, or WB back to ID (zero penalty). Nearest stage has priority.
Load-Use Hazard: Special type of RAW hazard. A lw produces its value in MEM, but the next instruction needs it in ID — forwarding alone can’t bridge this gap.
→ Stall 1 cycle (IF/ID stall, EX gets bubble), then forward from MEM.
Control Hazard (Branch Misprediction): Branch outcome isn’t known until EX stage. We predict not taken (fetch PC+4). If wrong: → 2-cycle penalty — inject bubbles into ID and EX to remove mispredicted instructions from the pipeline.
Pipeline Register Modes
- Normal: load new value
- Stall: hold current value
- Bubble: inject NOP
Performance
CPI = 1.0 + B/I (1 + bubbles per instruction)
Penalty = (fraction of that instruction type) × (hazard rate) × (bubble count). Typical CPI ≈ 1.2.